Reordering requests for access to subdivided resource

ABSTRACT

One embodiment comprises an apparatus for reordering requests for access to a subdivided resource. The apparatus includes a non-FIFO request buffer for temporarily storing the requests for access, a selector for selecting a next request from the request buffer, and a mechanism for outputting the next request to a controller for the resource. Another embodiment comprises a method for reordering requests for access to a subdivided resource. The method includes temporarily storing the requests for access, selecting a next request from among the stored requests in non-FIFO order, and outputting the next request to a controller for the resource.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] The present application is related to co-pending andcommonly-owned U.S. patent application Ser. No. 10/091,760 (Attorneydocket #100202161-1), filed Mar. 6, 2002, by inventor Jonathan M. Watts,and entitled “Re-Ordering Requests for Shared Resources,” the disclosureof which is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

[0002] 1. FIELD OF THE INVENTION

[0003] The present invention relates generally to electronic systems.More particularly, the invention relates to requests for access to aresource.

[0004] 2. DESCRIPTION OF THE BACKGROUND ART

[0005] Dynamic random access memory (DRAM) is an important form ofmemory. DRAM can store data with high density because a DRAM cellrequires as few as one transistor.

[0006] DRAM is commonly organized into memory banks. A single memorybank generally outputs the number of bits needed to fill the width of adata bus. For example, if the data bus is 32 bits wide, then a singlememory bank outputs 32 bits. If the data bus is 64 bits wide, then asingle memory bank outputs 64 bits. A multiple bank memory systemutilizes a plurality of memory banks. By using a plurality of memorybanks, memory accesses to different banks may be interleaved to increaseperformance by more fully utilizing the available data bus bandwidth.

[0007] In some memory systems, for example in synchronous DRAM (SDRAM)systems, a plurality of DRAM integrated circuits (often called “chips”)may be used to create a memory bank. In other memory systems, forexample in RDRAM developed by Rambus, Inc. of Los Altos, Calif., asingle DRAM chip may include multiple memory banks. In other systems,parts with multiple internal banks may be stacked to provide a widerword width.

[0008] Despite current advances in memories, as CPU and memory busspeeds continue to increase, further improvements in memory systems areneeded.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Non-limiting and non-exhaustive embodiments of the presentinvention are described in the Figures, in which:

[0010]FIG. 1 is a simplified diagram illustrating a type of DRAM chipthat includes multiple memory banks.

[0011]FIG. 2 is a flow chart depicting a conventional method forsupplying requests for access to a multiple bank memory system.

[0012]FIG. 3 is a diagram depicting an apparatus for reordering requestsfor access to a multiple bank memory in accordance with an embodiment ofthe invention.

[0013]FIG. 4A is a flow chart depicting a method for reordering requestsfor access to a multiple bank memory system in accordance with anembodiment of the invention.

[0014]FIG. 4B is another flow chart depicting a method for reorderingrequests for access to a multiple bank memory system in accordance withan embodiment of the invention.

[0015]FIG. 5 is a diagram depicting another apparatus for reorderingrequests for access to a multiple bank memory in accordance with anembodiment of the invention.

[0016]FIG. 6A is a diagram depicting a system including a reorderingapparatus external to a memory controller in accordance with anembodiment of the invention.

[0017]FIG. 6B is a diagram depicting a system including a reorderingapparatus internal to a memory controller in accordance with anembodiment of the invention.

[0018]FIG. 6C is a diagram depicting a system including a reorderingapparatus external to a memory controller and FIFO buffer(s) prior tothe reordering apparatus in accordance with an embodiment of theinvention.

[0019]FIG. 6D is a diagram depicting a system including a reorderingapparatus internal to a memory controller and FIFO buffer(s) prior tothe reordering apparatus in accordance with an embodiment of theinvention.

SUMMARY

[0020] One embodiment comprises an apparatus for reordering requests foraccess to a subdivided resource. The apparatus includes a non-FIFOrequest buffer for temporarily storing the requests for access, aselector for selecting a next request from the request buffer, and amechanism for outputting the next request to a controller for theresource. Another embodiment comprises a method for reordering requestsfor access to a subdivided resource. The method includes temporarilystoring the requests for access, selecting a next request from among thestored requests in non-FIFO order, and outputting the next request to acontroller for the resource.

DETAILED DESCRIPTION

[0021]FIG. 1 is a simplified diagram illustrating a type of memory thatincludes multiple memory banks. The hypothetical DRAM chip depicted inFIG. 1 is merely an example of a type of memory with which the presentinvention may be used. Those familiar with memory architectures willrecognize that the example multiple bank DRAM depicted in FIG. 1 isanalogous in configuration to Rambus DRAMs (“RDRAMs”) developed byRambus, Inc. of Los Altos, Calif. Actual RDRAMs developed by Rambus, ofcourse, have various differences. For example, it may have 32 memorybanks (not the 16 memory banks of FIG. 1). There are various versions ofRDRAM including 72 megabit (Mbit), 144 Mbit, and 288 Mbit versions.

[0022] The present invention may also be used with other types ofmemory. For example, the present invention is applicable to synchronousDRAMs (“SDRAMs”) and double data rate (“DDR”) SDRAMs as they also havemultiple banks (typically four, for example). Application of the presentinvention to these other types of memory may be more straightforwardbecause of the absence of certain peculiarities of RDRAMs (such as theshared sense amplifier configuration of RDRAMs).

[0023] Furthermore, the present invention may also be applied to reorderrequests to other types of resources (not just memory). Other types ofresources may have subdivisions similar to or analogous to the banks ofmemory.

[0024] Returning to FIG. 1, a multiple bank DRAM chip 100 that includessixteen memory banks is depicted. The memory banks being labeled “Bank0” 102-0 through “Bank 15” 102-15. Of course, sixteen is merely anexample of a number of banks. The number of banks may be just as easilya different number (for example, four, eight, thirty-two, sixty-four,and so on).

[0025] The particular multiple bank DRAM 100 depicted in FIG. 1 includestwo data buses, one to the left 104 a and one to the right 104 b. Thetwo data out buses 104 a and 104 b each run the length of the sixteenmemory banks (102-0 through 102-15). Seventeen groups of senseamplifiers 106 are shown between the memory banks 102 and the data buses104. The groups of sense amplifiers are labeled 0, 0/1, 1/2, . . .14/15, and 15.

[0026]FIG. 2 is a flow chart depicting a conventional method forsupplying requests for access to a multiple bank memory system. Theconventional method 200 as depicted in FIG. 2 includes just two steps(202 and 204).

[0027] In the first step 202, the requests may be buffered by afirst-in-first-out (FIFO) buffer. This buffering allows requests toaccess memory to be received and to be put into a queue even while thememory is busy.

[0028] In the second step 204, the next request (the oldest one in theFIFO buffer) is output to the memory controller. The memory controllerthen processes the request.

[0029] Hence, memory requests to multiple bank memory systems areconventionally serviced in the order in which the requests are received.This can lead to idle time for the data bus if the next request needs toaccess an active memory bank (i.e., one already being accessed).

[0030] For example, referring to FIG. 1, each bank contains a number of“rows” of data. The sense amplifiers can hold the data from one row. Inthe 72 Mbit version of RDRAM, each row contains 9216 bits, each bank has512 rows. If data is requested from a bank which is active, but not fromthe row that is active, then the controller would have to wait untilaccess of the active row is complete prior to accessing the requestedrow.

[0031]FIG. 3 is a diagram depicting an apparatus for reordering requestsfor access to a multiple bank memory in accordance with an embodiment ofthe invention. The apparatus 300 as depicted in FIG. 3 includes arequest buffer 302, a selector 304, an access history circuit 306, and amultiplexor (MUX) 308.

[0032] The request buffer 302 comprises a non-FIFO buffer fortemporarily storing requests received from one or more memory user(s).The number of requests that can be stored in the request buffer 302 maybe dictated by he needs of a particular system. The greater the numberof requests which can be stored in the Request Buffer 302, the higherthe efficiency that can be achieved. However, a greater number ofrequests may also increase the cost, the difficulty of the job of theSelector 304, and the variability of the service latency. For example,in one specific implementation, two request buffers may be used: one forread requests and one for write requests. In this example, each requestbuffer can hold up to eight requests. Pipelining may be implemented inthe controller so that several additional requests may be in process atany given time.

[0033] While the request buffer 302 is not a FIFO buffer, it may bedesirable to maintain the order in which the requests were received inthe buffer 302. However, the order in which requests are taken would bea different order that is non-FIFO and to be determined by the selector304.

[0034] The selector 304 selects a next request from the request buffer302. In one embodiment, the selector 304 may use a history of recentmemory accesses in determining the next request to select. The historyof recent memory accesses may be provided by the access history circuit306. The history of recent memory accesses may comprise recent requeststhat were output by the multiplexor 308 to the memory controller.

[0035] The selector 304 may include logic to select the next request insuch a way as to avoid, if possible, the need to wait during memory bankrecovery time (delay after the data transfer) and/or during memory bankaccess time (delay before the data transfer). This criterion forselecting the next request may be called the bank conflict avoidancecriterion or simply the conflict avoidance criterion. For example, theselector 304 may prioritize (favor) the selection of a next request thatneeds to access only currently inactive memory banks (over requests thatrequire accessing currently active memory banks). If bank conflicts areavoided, then typically both the access time (before the data transfer)and the recovery time (after the data transfer) may be “hidden” bypipelining (overlapping requests) so that those times do not adverselyaffect performance.

[0036] In one embodiment, if two or more requests are rated as equalbased on the conflict avoidance criterion, then the selector's logic mayfavor the selection of the oldest request of the equally rated requests.In addition, the selector's logic may disfavor (lower priority of) thoserequests that would result in a conflict (accessing different banks)than one or more of the oldest requests. These two additional criteriahelp ensure forward progress of requests in the buffer 302 and prevent“starvation” of any memory user in that no request is forced to waitforever before access is granted.

[0037] In order for the selector 304 to properly make these selectiondecisions, it uses information about the structure and behavior of thememory system. That is, the selector 304 makes use of or appliesinformation about which memory bank(s) is (are) affected by each requestfor memory access. In addition, the selector 304 makes use of or appliesinformation about time intervals during which the affected memory bankswill be unable to begin processing another request. Of course, thespecific banks affected by a request and unusable time intervals aredependent on the specific system.

[0038] The following cycle description is representative only and givenfor purposes of illustration. The cycle described may not exactlycorrespond to a cycle from an actual memory part. First, a specificamount of time (e.g., 3 clock cycles) is typically required to activatea row of a bank by reading data from the row into the sense amplifiers.Second, a specific amount of time (e.g., 2 clock cycles) is typicallyrequired to read a particular word from the active row. Third, aspecific amount of time (for example 2 clock cycles) is typicallyrequired for recovery time after the last word is read before a new rowactivation can be initiated. For example, the following may occur in thereading of four words from a single row of a bank: Cycle Activity 1activate row 2 wait for activate to complete 3 wait for activate tocomplete 4 initiate read of word 1 5 initiate read of word 2 6 initiateread of word 3; word 1 is on data bus 7 initiate read of word 4; word 2is on data bus; initiate close of bank 8 word 3 is on data bus; wait forbank to close 9 word 4 is on data bus; can perform another rowactivation

[0039] An optional technique which the selector 304 may employ is tomake no selection on a cycle if none of the currently available requestsin the buffer 302 could begin processing immediately by the memorysystem. For such cycles, since no request present in the buffer 302could be started, deferring the selection of the next request does notcost performance (i.e., does not add further delay). This techniqueprovides for the possibility that a new request may arrive which couldbe processed sooner than any of the requests currently present in thebuffer 302. In order to implement this technique, a valid request signalmay be sent to the memory controller so that a non-valid request may beindicated during cycles when no request is selected. This optional validrequest signal is indicated by the dashed line in FIG. 3 from theselector 304 to the memory controller.

[0040] Once the selector 304 has determined which is the next request tobe serviced, it controls the multiplexor 308 to output (make available)the next request to the memory controller. The multiplexor 308 mayoutput the next request by selecting the line(s) associated with thestorage of the next request in the buffer 302.

[0041] In addition, the selector 304 also notifies the non-FIFO requestbuffer 302 that the next request was taken so that the next request maybe removed from the buffer 302. If required, the selector 304 alsoindicates a valid request to the memory controller.

[0042] The request buffer 302 removes the request which has been taken.The buffer 302 may also perform re-arrangement of requests withinitself. For example, in one implementation, the remaining requests maybe moved so as to keep all the requests contiguous and correctly orderedin the buffer 302.

[0043]FIG. 4A is a flow chart depicting a method for reordering requestsfor access to a multiple bank memory system in accordance with anembodiment of the invention. The method 400 as depicted in FIG. 4Aincludes three steps (402, 404, and 406).

[0044] In the first step 402, the requests for access are storedtemporarily. The requests for access may be requests for memory accessreceived from one or more memory user(s). The temporary storage may bedone in a non-FIFO request buffer 302. Requests may be added to thenon-FIFO request buffer 302 when another request for access is receivedand there is space available in the buffer 302.

[0045] In the second step 404, the next request is selected from thetemporary storage. The selection of next requests may be done innon-FIFO order in that the first in does not have to be the first out.The selection may be done by a selector 304. Embodiments of theselection step 404 performed by the selector 304 are described in moredetail above in relation to FIG. 3.

[0046] In the third step 406, the next request is output to the memorycontroller. The outputting of the next request may be done by amultiplexor 308.

[0047]FIG. 4B is another flow chart depicting a method for reorderingrequests for access to a multiple bank memory system in accordance withan embodiment of the invention. The method 450 as depicted in FIG. 4Bincludes five steps (452, 402, 404, 406, and 454).

[0048] In the first step 452, the requests for access may be buffered.The requests for access may be requests for memory access received fromone or more memory user(s). The buffering may be done, for example,using a FIFO buffer. The FIFO buffer may then pass the requests to thenon-FIFO buffer 302 for temporary storage as described in the secondstep 402.

[0049] In the second step 402, the requests for access are storedtemporarily in the non-FIFO request buffer 302. Requests may be added tothe request buffer 302 when the FIFO buffer has a request to provide andthe request buffer 302 has space available for the request.

[0050] In the third step (the selection step) 404, the next request isselected from the temporary storage. The selection of next requests maybe done in non-FIFO order in that the first in does not have to be thefirst out. The selection may be done by a selector 304.

[0051] In the fourth step (the output step) 406, the next request isoutput to the memory controller. The outputting of the next request maybe done by a multiplexor 308.

[0052] In the fifth step 454, a history of recent accesses may bederived and fed back to the selection step 404. In one embodiment, thehistory of recent accesses may comprise recent next requests output inthe output step 406.

[0053]FIG. 5 is a diagram depicting another apparatus for reorderingrequests for access to a multiple bank memory in accordance with anembodiment of the invention. The apparatus 500 as depicted in FIG. 5includes multiple buffers 502 (502 a, 502 b, . . . , 502 n), a selector504, an access history circuit 506, and a multiplexor (MUX) 508.

[0054] The operation of the apparatus 500 in FIG. 5 is similar to theoperation of the apparatus 300 in FIG. 3. However, the apparatus 500 ofFIG. 5 illustrates an embodiment where multiple request buffers 502 (502a, 502 b, . . . , 502 n) receive requests from memory users.

[0055] In such an apparatus 500 with multiple request buffers 502, theselector 504 may utilize additional criteria for selecting betweenrequests in the multiple buffers 502. For example, a round robincriterion may be used such that the next request is selected from abuffer 502 during that buffer's turn as assigned by the round robin.Another possible additional criterion would assign priorities to thedifferent buffers 502 such that the next request is selected from ahigher priority buffer 502 prior to being selected from a lower prioritybuffer 502. Another possible additional criterion would be to use onebuffer 502 for as long as that buffer 502 has more requests, then switchbuffers 502 when that buffer 502 has no more requests left.

[0056] In the above description, numerous specific details are given toprovide a thorough understanding of embodiments of the invention.However, the above description of illustrated embodiments of theinvention is not intended to be exhaustive or to limit the invention tothe precise forms disclosed. One skilled in the relevant art willrecognize that the invention can be practiced without one or more of thespecific details, or with other methods, components, etc. In otherinstances, well-known structures or operations are not shown ordescribed in detail to avoid obscuring aspects of the invention. Whilespecific embodiments of, and examples for, the invention are describedherein for illustrative purposes, various equivalent modifications arepossible within the scope of the invention, as those skilled in therelevant art will recognize.

[0057]FIG. 6A is a diagram depicting a system including a reorderingapparatus external to a memory controller in accordance with anembodiment of the invention. The system 600 as depicted includes one ormore memory user(s) 602, a reordering apparatus 300 or 500, a memorycontroller 604, and memory (DRAM) banks 606. In the embodiment shown inFIG. 6A, the reordering apparatus 300 or 500 is external to the memorycontroller 604.

[0058]FIG. 6B is a diagram depicting a system including a reorderingapparatus internal to a memory controller in accordance with anembodiment of the invention. The system 610 as depicted includes one ormore memory user(s) 602, a reordering apparatus 300 or 500, a memorycontroller 612, and memory (DRAM) banks 606. In the embodiment shown inFIG. 6B, the reordering apparatus 300 or 500 is integrated into thememory controller 604.

[0059]FIG. 6C is a diagram depicting a system including a reorderingapparatus external to a memory controller and FIFO buffer(s) prior tothe reordering apparatus in accordance with an embodiment of theinvention. The system 620 as depicted includes one or more memoryuser(s) 602, FIFO buffer(s) 622, a reordering apparatus 300 or 500, amemory controller 604, and memory (DRAM) banks 606. The system 620 inFIG. 6C is similar to the system 600 in FIG. 6A, but the system 620 inFIG. 6C includes FIFO buffer(s) 622 in place prior to the reorderingapparatus 300 or 500.

[0060]FIG. 6D is a diagram depicting a system including a reorderingapparatus internal to a memory controller and FIFO buffer(s) prior tothe reordering apparatus in accordance with an embodiment of theinvention. The system 630 as depicted includes one or more memoryuser(s) 602, FIFO buffer(s) 622, a reordering apparatus 300 or 500, amemory controller 632, and memory (DRAM) banks 606. The system 630 inFIG. 6D is similar to the system 610 in FIG. 6B, but the system 630 inFIG. 6D includes FIFO buffer(s) 622 in place prior to the reorderingapparatus 300 or 500. FIG. 6D has these FIFO buffers 622 integrated intothe memory controller 632. Alternatively, the FIFO buffers 622 may beexternal to the memory controller 632.

[0061] The following discussion is meant to illustrate how the presentinvention may be used to advantage. The efficiency numbers in thediscussion are meant to be rough based on various simplifyingassumptions. This discussion of efficiency is meant for purposes ofillustration only and not to be limiting. To a first order (rough)approximation, the probability of encountering a bank conflict with ahypothetical 16 bank RDRAM using conventional techniques would be{fraction (3/16)} or about 19%. Such a bank conflict will cause a waitfor the conflict to clear (which may be, for example, eight clockcycles). Utilizing the re-ordering of the invention, the probability ofa bank conflict may be reduced to roughly {fraction (3/16)} raised tothe nth power [({fraction (3/16)})^(n)], where n is the number ofentries in the request buffer from which the next request may beselected. For example, if there are eight entries in the request buffer,then the probability of a conflict would be roughly ({fraction(3/16)})⁸=less than 1%. For purposes of simplicity, consider that thememory transactions are eight words long. Then the memory efficiencywithout the invention may be roughly:$\frac{8}{8 + {8\left( {3/16} \right)}} = {84\quad \%}$

[0062] On the other hand, with the re-ordering of the invention, andmaking several assumptions such as assuming eight entries in the requestbuffer, then the memory efficiency may be roughly:$\frac{8}{8 + {8\left( {3/16} \right)^{8}}} = {{over}\quad 99\quad \%}$

[0063] Similarly, a 4 bank SDRAM may have an efficiency without theinvention of roughly:$\frac{8}{8 + {8\left( {1/4} \right)}} = {75\quad \%}$

[0064] With the re-ordering of the invention (and the same or similarassumptions as above), the efficiency may be improved to roughly:$\frac{8}{8 + {8\left( {1/4} \right)^{8}}} = {{over}\quad 99\quad \%}$

[0065] Per the above, the efficiency improvement increases as the numberof banks decrease. The efficiency improvement also increases when thebank conflict penalty increases or the transfer length decreases. Notethat the above approximation formula breaks down when the transferlength is less than the bank conflict penalty. Nevertheless, theconclusion that efficiency is improved is the point of the discussionand should remain valid.

[0066] These modifications can be made to the invention in light of theabove detailed description. The terms used in the following claimsshould not be construed to limit the invention to the specificembodiments disclosed in the specification and the claims. Rather, thescope of the invention is to be determined by the following claims,which are to be construed in accordance with established doctrines ofclaim interpretation.

What is claimed is:
 1. An apparatus for reordering requests for accessto a subdivided resource, the apparatus comprising: a non-FIFO requestbuffer for temporarily storing the requests for access; a selector forselecting a next request from the request buffer; and a mechanism foroutputting the selected request to a controller for the resource.
 2. Theapparatus of claim 1, the apparatus further comprising: an accesshistory module for providing a history of recent accesses to theselector for use in determining the next request.
 3. The apparatus ofclaim 2, wherein the history of recent accesses comprises recentrequests output by the mechanism.
 4. The apparatus of claim 1, whereinthe non-FIFO request buffer maintains the requests in a same order asreceived but outputs the requests in a different order determined by theselector.
 5. The apparatus of claim 1, the apparatus further comprising:a FIFO request buffer for receiving the requests for access and forproviding the requests to the non-FIFO request buffer.
 6. The apparatusof claim 1, wherein the selector includes logic to select the nextrequest based on a conflict avoidance criterion so as to avoid a need towait during resource subdivision related delay time.
 7. The apparatus ofclaim 6, wherein the selector favors an oldest request if two or morerequests are rated as equal based upon the conflict avoidance criterion.8. The apparatus of claim 6, wherein the selector disfavors requeststhat would result in a conflict with one or more of the oldest requests.9. The apparatus of claim 1, wherein the selector has information aboutwhich resource subdivision is (are) affected by each request for access.10. The apparatus of claim 9, wherein the selector has furtherinformation about time intervals during which the affected resourcesubdivision will be unable to begin processing another request.
 11. Theapparatus of claim 1, wherein the selector outputs a valid requestindicator so that a non-valid request may be indicated if no nextrequest is selected for a particular cycle.
 12. The apparatus of claim1, wherein the mechanism comprises a multiplexor, and wherein theselector controls the multiplexor to output the next request.
 13. Theapparatus of claim 12, wherein the selector notifies the non-FIFOrequest buffer that the next request was taken so that next request maybe removed from the non-FIFO request buffer, and wherein the non-FIFOrequest buffer rearranges remaining requests therein.
 14. The apparatusof claim 1, wherein the apparatus comprises circuitry between thecontroller and one or more source(s) of the requests for access.
 15. Theapparatus of claim 1, wherein the apparatus comprises circuitryincorporated into the controller, and wherein the next request is outputto other circuitry in the controller.
 16. A method for reorderingrequests for access to a subdivided resource, the method comprising:temporarily storing the requests for access; selecting in non-FIFO ordera next request from among the temporarily stored requests; andoutputting the next request to a controller for the resource.
 17. Themethod of claim 16, the method further comprising: providing a historyof recent accesses to be used in selecting the next request.
 18. Themethod of claim 17, wherein the history of recent accesses comprisesrecent requests output to the controller.
 19. The method of claim 16,wherein the temporarily stored requests are maintained in a same orderas received but may be output to the controller in a different order.20. The method of claim 16, the method further comprising: buffering therequests for access in a first-in-first-out order prior to temporarilystoring the requests.
 21. The method of claim 16, wherein the nextrequest is selected based on a conflict avoidance so as to avoid anunnecessary need to wait.
 22. The method of claim 21, wherein an oldestrequest is favored if two or more requests are judged equal based on theconflict avoidance.
 23. The method of claim 21, wherein requests aredisfavored that would result in a conflict with one or more of theoldest requests.
 24. The method of claim 16, wherein selecting the nextrequest depends on information about which resource subdivision(s) is(are) affected by each request for access.
 25. The method of claim 24,wherein selecting the next request further depends on information abouttime intervals during which the affected resource subdivision(s) will beunable to process another request.
 26. The method of claim 16, wherein avalid request indicator is output to the controller so that a non-validrequest may be indicated if no next request is selected for a particularcycle.
 27. The method of claim 24, wherein the resource comprises amultiple bank memory system, wherein a resource subdivision comprises amemory bank, and wherein a request for access comprises a request formemory access.
 28. A multiple bank memory system including requestreordering, the system comprising: a multiple bank memory; a memorycontroller; means for temporarily storing requests for access to themultiple bank memory; means for selecting a next request from among thestored requests in non-FIFO order; and means for outputting the nextrequest to the memory controller.
 29. An apparatus for reorderingrequests for access to a multiple bank memory, the apparatus comprising:a plurality of non-FIFO request buffers for temporarily storing therequests for access; a selector for selecting a next request from theplurality of non-FIFO request buffers; and a multiplexor for receivingthe next request and outputting the next request to a memory controller.30. The apparatus of claim 29, wherein the selector includes logic thatutilizes a round robin type algorithm in selecting the non-FIFO requestbuffer from which the next request will be selected.
 31. The apparatusof claim 29, wherein the selector includes logic that favorssequentially selecting requests from a same non-FIFO request buffer anddisfavors switching buffers in selecting requests.
 32. The apparatus ofclaim 29, wherein the selector prioritizes non-FIFO request buffers inselecting the next request.